A Novel Modular Reduction Approach to Reduce the Delay for High-throughput Computation, and Low Latency

Recently, finite field multipliers having high throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such multipliers over GF(2) for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and highthroughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of , where is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to TA+TX,TA being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce areacomplexity of BP-I and BP-II further INTRODUCTION Finite Field multiplication over operation, which is frequently used in elliptic curve cryptography is a basic field (ECC) to perform pointadditions and point-doubling operations on an elliptic curve. The irreducible Pentanomials have been popularly used to generate binary extension fields to be used in ECC. Moreover, National Institute of Standards and Technology (NIST)has recommended three pentanomials for ECC implementation. Several efforts have therefore been made on efficient realization of multiplication over GF(2) based on irreducible Pentanomials. Systolic designs provide area-time efficient implementation due to modularity and regularity of their structures, where each processing element (PE) has the same or similar circuit design, and one PE can pass the signals to its neighboring PE at a high speed on a fully pipelined path. The traditional LSD-first multiplication given by (2) can be described by Algorithm 1. Fig. 1 shows a digit-serial multiplier over GF(2m) based on Algorithm 1. It consists of one multiplier core, two registers for two reduction Figure. Traditional LSD-first digit-serial multiplier Montgomery multiplication is a method for computing ab mod m for positive integers a, b, and m. It reduces execution time on a computer when there are a large number of multiplications to be done with the same modulus m, and with a small number of multipliers. Volume 5, Issue 5 DEC 2016 IJRAET Montgomery multiplication is a method for computing ab mod m for positive integers a, b, and m. 1 It reduces execution time on a computer when there are a large number of multiplications to be done with the same modulus m, and with a small number of multipliers.